The present invention relates to semiconductor technologies, and more particularly to manufacturing methods for the fabrication of semiconductor devices.
In the field of semiconductor technology, the embedded flash (E-flash) memory fabrication process is often combined with the manufacturing process for logic devices. Flash memory devices and logic devices have different technical requirements, and therefore there are often trade-offs in combining the manufacturing processes for these two types of devices.
FIGS. 1A, 1B, 1C, 1D, and 1E are cross-sectional view diagrams illustrating a conventional manufacturing method of a semiconductor device. As shown, a conventional method of manufacturing a semiconductor device can include the following steps:
Step E1: successively form a silicon oxide layer 101 and a silicon nitride layer 102 on a semiconductor substrate 100, and etch silicon nitride layer 102, silicon oxide layer 101, and semiconductor substrate 100 to form a trench, as shown in FIG. 1A.
Step E2: fill trench 1030 with a dielectric material (typically silicon oxide) and perform CMP (chemical mechanical polish) to form a shallow trench isolation (STI) as shown in FIG. 1B.
Step E3: remove silicon nitride layer 102, shown in FIG. 1C.
Step E4: deposit a floating gate material layer 1040 (typically polysilicon), as shown in FIG. 1D. Step E5: perform CMP on floating gate material layer 1040 to form floating gates 104, as shown in FIG. 1E.
The inventor has observed that in the conventional technology, the thickness of silicon nitride layer 102 is usually 1.5 to 2 times the final thickness of floating gate 104. The relatively large thickness of silicon nitride 102 can result in a high aspect ratio in the filler dielectric material in step E2, which often leads to the formation of cavities 1031 in shallow trench isolation 103, as shown in FIG. 1B. Similarly, floating gate 104 is also prone to cavities 1041, as shown in FIG. 1D.
In the technical field, in order to ensure device performance, shallow trench isolation 103 and the floating gate 104 should be free from voids. The inventor has determined that the main consideration here is critical dimensions and aspect ratio in filling the trench. Generally speaking, large size AA (active area) regions can lead to voids in a shallow trench isolation, and in the use of self-aligned method of forming a floating gate material layer, small size AA can lead to voids within the floating gate. Thus, in order to ensure that the internal shallow trench isolation and the floating gate are free from voids, there is a need to balance the formation of shallow trench isolation and the formation of floating gate, which has a relatively narrow process window. In conventional technologies, it is often difficult to prevent voids in shallow trench isolation and the floating gate at the same time. FIGS. 2A and 2B are scanning electron microscope (SEM) photographs illustrating voids formation in conventional technologies.
In addition, the inventor has also observed severe loading effects in the CMP process of the floating gate layer between a memory cell area and the pad area. As illustrated in the SEM photograph in FIG. 2C, the floating gate in the pad region can exhibit a relatively loss of thickness (1051), which can result in damages in the AA area 1061.
Thus, the conventional method of manufacturing a semiconductor device cannot simultaneously prevent voids formation inside shallow trench isolation and the floating gate. Further, in the conventional method, the loading effect in the CMP process often causes problems in floating gate topography. Thus, it is desirable to develop a new method of manufacturing semiconductor devices.